The present invention relates to forming conductive layers on insulators by physical vapor deposition (PVD).
FIG. 1 illustrates a conventional physical vapor deposition chamber 110 used to deposit conductive layers on a semiconductor wafer 120 in the process of fabrication of integrated circuits. The wafer is placed on a pedestal 130 at the bottom of the chamber. A target 140 is mounted at the top of the chamber and biased by a DC bias source 150. Argon or some other plasma forming gas is flown into chamber 110 and is ionized by an electrical field that can be created by the potential difference between wafer 120 and target 140, or by a separate coil 160. Due to the target bias created by source 150, the argon ions accelerate towards target 140 and dislodge molecules from the target. These sputtered molecules settle on wafer 120. (In a xe2x80x9creactivexe2x80x9d physical vapor deposition, the sputtered molecules can undergo a chemical reaction before settling on the wafer; for example titanium molecules may react with nitrogen to form titanium nitride which is then deposited on the wafer.)
Some of the sputtered molecules settle on the walls of the chamber and not on the wafer. To increase the number of the molecules settling on the wafer, the molecules are ionized, and the wafer is biased to attract the ionized molecules (these ions are shown at 140i). In particular, in FIG. 1, coil 160 densifies the argon plasma in chamber 110, and this high density plasma causes at least some of the sputtered molecules to become ionized. (The plasma can eventually be sustained by ions 140i; the argon flow into the chamber can be turned off.) The wafer is biased by an AC or DC bias source 170 to attract the ions 140i. The bias from source 170 can be applied to the wafer or, alternatively, to pedestal 130 whose top surface can be made from an insulating material. This technique (ionizing the molecules sputtered from the target) is known as ionized physical vapor deposition (I-PVD) or ionized metal plasma deposition (IMP). An example IMP chamber 110 is a magnetron sputtering chamber of type Vectra available from Applied Materials of Santa Clara, Calif. as part of a system of type ENDURA(copyright). The Vectra chamber is operated with bias source 170 providing an RF bias (13.56 MHz) applied to pedestal 130 having an insulating top surface, with bias source 150 providing a DC bias, and with coil 160 carrying an RF current (13.56 MHz).
Ionized PVD has particular advantages for contact fabrication. FIG. 2 illustrates a typical contact structure that can be fabricated in wafer 120. Conductive layer 210 is part of a semiconductor substrate (e.g. monocrystalline silicon), or is formed over a semiconductor substrate. Insulator 220 (e.g. silicon dioxide) is formed over layer 210. Contact opening 224 in insulator 220 exposes the layer 210. A conductive layer 230 is deposited by I-PVD over insulator 220 and into opening 224. Layer 230 can provide an interconnect contacting the layer 210 through opening 224. Layer 230 can also provide as an adhesion or barrier layer separating an overlying conductive layer (not shown) from layer 210. For example, layer 230 can be a titanium or titanium nitride layer separating an overlying aluminum or tungsten layer from silicon or metal layer 210.
Ionized PVD is a good method for fabrication of layer 230 because the wafer bias causes the ions 140i to travel in a direction normal to the wafer. Deposition into deep openings 224 is therefore facilitated. Also, good sidewall coverage is achieved in the opening due to re-sputtering of layer 230. More particularly, as illustrated in FIG. 2, ions 140i may dislodge previously deposited molecules 230a from layer 230. Some of the dislodged molecules 230a settle on the sidewalls and the bottom of opening 224, improving the sidewall and bottom coverage. In addition, for some materials 230, a significant portion of the dislodged molecules 230a comes from the top edges 224E of opening 224. Consequently, it is more difficult for the deposited material to form overhangs at the top edges of the opening, and hence deposition into the opening is further facilitated. See xe2x80x9cHandbook of Semiconductor Manufacturing Technologyxe2x80x9d (edited by Yoshio Nishi et al., 2000), pages 409-410, incorporated herein by reference.
The inventor has observed that at the beginning of the deposition, when insulator 220 is exposed, ions 140i can dislodge the insulator molecules, and the insulator molecules can settle on layer 210. This undesirably increases the contact resistance.
According to one embodiment of the present invention, the wafer bias at the beginning of the deposition is set to zero. After some period (a few seconds in some embodiments), the wafer bias is increased. At this time, insulator 220 has been at least partially covered by material 230, so dislodging of the insulator molecules is unlikely.
In some embodiments, the wafer bias at the beginning of the deposition is not zero but is lower than at a later stage of the deposition.
Another technique that may reduce the possibility of the xe2x80x9cinsulator re-sputteringxe2x80x9d (dislodging of the insulator molecules) is reducing the power in coil 160 at the beginning of the deposition, or reducing the target bias generated by source 150. Other embodiments are within the scope of the invention, as defined by the appended claims.